1. Field of the Invention
The invention relates to a gallium nitride (GaN) epitaxial growth method, and more particularly to a gallium nitride epitaxial growth method of a flexible nano-imprint.
2. Related Art
Performing structure epitaxy and process of a power device on a GaN epitaxy substrate, which is homogeneous and has the matched property, is advantageous to the creating of the device indicator property. Using the heterogeneous substrate (e.g., Sapphire, Si, or the like) is advantageous to the reduction of the research, development and manufacturing costs. However, due to the influence of the property mismatch, the “low-defect” heterogeneous epitaxy technology has to be further researched and developed. The lattice constant and thermal expansion coefficient differences, induced by the heterogeneous epitaxy, inevitably affect the epitaxy structure quality, thereby causing the defects and stresses of the epitaxial layer. In the device application, the pressure resistance of the device is seriously affected, and the epitaxial layer stress causes the wafer warpage and affects the device processing precision. In the large-scale wafer, especially the MOCVD epitaxy technology of growth at the high temperature, this phenomenon becomes more serious. Taking the Si substrate as an example, the lattice mismatch between Si and GaN is as high as 16.2%, the difference between the thermal expansion coefficients of Si and GaN is as high as 113%, and the disadvantageous factor, such as the high reaction activity between Si and nitrogen (N) atoms. Thus, the MBE epitaxy technology adopting the low-temperature growth is a key issue for implementing the low-defect heterogeneous epitaxy technology. If the vertical device is to be implemented, then the pressure resistance is extremely associated with the thickness (more than 4 microns) and the quality of the GaN epitaxial layer.
The epitaxy technology, either the molecule beam epitaxy (MBE) or the metal organic chemical vapor deposition (MOCVD), has implemented the epitaxy growth of hexagonal structure gallium nitride (GaN) on the Si (111) substrate. In the example reference [C. W. Nieh, Y. J. Lee, W. C. Lee, Z. K. Yang, A. R. Kortan, M. Hong, J. Kwo, and C. H. Hsu, Appl. Phys. Lett., 92, 061914 (2008)], a well-crystallized monocrystalline oxide layer with several nanometers is firstly deposited on the Si (111), and serves as the epitaxy pattern bottom of the monocrystalline GaN, wherein this pattern bottom can effective prevent the mutual diffusion between Si and GaN and is also a key seeding layer for the growth of GaN. Considering the mainstream silicon wafer technology and the potential of the future integrated III-N and silicon device, Si (001) is the more pragmatic and preferred choice. In addition, compared with the current generic hexagonal wurtzite structure, the III-N of the cubic zinc-blende structure has the advantages of the non-polarization, the high quantum efficiency and the high p-type conductivity. However, growing GaN on Si (001) makes the growth of GaN have multiple preferred orientations due to the plane symmetry difference, thereby causing the polycrystalline structure or coarse surface. In addition, the above-mentioned thermal expansion coefficient difference and lattice mismatch also cause the epitaxial layer to have the high threading dislocation (TD) density or even to form crack networks. In order to decrease the TD density, the III-N LED industry conventionally performs the pre-patterning on the sapphire epitaxy substrate. The same method is also applied to the Si (111) substrate. It is to be emphasized that the feature size of this conventional patterning process pertains to the micron (μm) level. Recently, by adopting the nanometer (nm) level patterning process, the TD density of the GaN epitaxial layer can be further reduced. This is because the nano-scale epitaxy structure dimension is advantageous to the decrease of the strain energy accumulated by the mismatched lattices, thereby decreasing the possibility of generating defects.